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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Table 8. XGXS Registers (Continued)
Bit(s)
Name
Description
R/W
Reset Value
0 = Low Power Mode
4.0.11
Low Power
1 = Normal operation This bit is connected to the
R/W
1
ORT82G5 “PASB_PDN” signal.
4.0.[10:7]
Reserved
Value always 0
R
0
4.0.6
Speed Selection
Value always 0
R
0
4.0.[5:2]
Speed Selection
Value always 0
R
0
4.0.[1:0]
Reserved
Value always 0
R
0
Status 1 Registers
4.1.[15:8]
Reserved
Value always 0
R
0
4.1.7
Fault (Not Supported)
0 = No Fault condition
R
0
4.1.[6:3]
Reserved
Value always 0
R
0
1 = Link is up, 0 = Link is down Writing to this bit sets
4.1.2
PHY XS TX link status
the corresponding ORT82G5 register bits:
CH A = 30814[5]
R
0
CH B = 30914[5]
4.1.1
Low Power Ability
1 = Low Power Mode support
R
1
4.1.0
Reserved
Value always 0
R
0
XGXS Identi ? er Registers
4.2:[15:0]
PHY XS Identi ? er
MSB = 0x0000
R
0
4.3:[15:0]
PHY XS Identi ? er
LSB = 0x0004
R
0004
XGXS Reserved Registers
4.4.[15:1]
Reserved
Value always 0
R
0
4.4.0
10 G Capable
Value always 1
R
1
Status 1 Registers
4.5.[15:6]
Reserved
Value always 0
R
0
4.5.5
DTE XS Present
Value always 0
R
0
4.5.4
PHY XS Present
Value always 1
R
1
4.5.3
PCS Present
Value always 0
R
0
4.5.2
WIS Present
Value always 0
R
0
4.5.1
PMD/PMA Present
Value always 0
R
0
4.5.0
Clause 22 regs present
Value always 0
R
0
XGXS Reserved Registers
4.6.15
Vendor speci ? c device present Value always 0
R
0
4.6.[14:0]
Reserved
Value always 0
R
0
XGXS Reserved Registers
4.8.[15:14]
Device present
10 = Device responding to this address
R
10
4.8.[13:12]
Reserved
Value always 0
R
0
4.8.11
Transmit Fault
(Not Supported)
0 = No fault of tx path
R
0
4.8.10
Receive Fault
(Not Supported)
0 = No fault of tx path
R
0
4.8.9:0
Reserved
Value always 0
R
0
4.15, 4.14
Package Identi ? er
Value always 0
R
0
XGXS Reserved Registers
4.24.[15:13] Reserved
Value always 0
R
0
18
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